Phase locked loops are used to generate an output signal with a defined phase relationship with an input reference signal. The output signal is matched to the phase of the input reference signal by a feedback loop in which the phase difference between the input reference signal and the output signal is determined by a phase detector. In an analog phase locked loop, the phase detector provides an analog output to an analog loop filter, which in turn provides an input to a voltage controlled oscillator, which causes the frequency of the oscillator to track the reference signal by maintaining a fixed phase relationship therewith. In a digital phase locked loop, a time to digital converter (TDC) may be used to determine a timing difference between the output from a frequency controlled oscillator and the reference signal. The loop filter in a digital phase locked loop may be a digital loop filter. In some digital phase locked loops, a numerically controlled oscillator may be used. An all-digital phase locked loop comprises a digital detector for determining the phase difference, a digital loop filter and a numerically controlled oscillator.
The resolution and noise characteristics of a TDC for use in a phase locked loop is important in determining the performance characteristics of the phase locked loop.
Time to digital converters used in prior art high performance phase locked loops typically comprise a cascade of delay elements (e.g. a gated ring oscillator, as described in C.-M. Hsu, M. Z. Straayer, and M. H. Perrott, “A Low-Noise Wide-BW 3.6-GHz Digital SD Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation,” IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp. 2776-2786, December 2008.) In such an architecture a problematic ground bounce is typically generated by sampling flip-flops of the TDC due to the unary coded (thermometer coded) nature of the delay line. In order to provide sufficient dynamic range, the TDC dynamic range is extended by using a counter to count a phase wrapping of the TDC. If the stop signal coincides with the counter clock, the phase information may be corrupted. Furthermore, good matching of the characteristics of each delay element is necessary to avoid errors in delay matching. Both the load capacitance and active part of each delay element are important for delay matching. It is challenging to obtain sufficiently good matching to obtain low noise characteristics from the TDC.
A prior art time to digital converter comprising a successive approximation register analog to digital converter is disclosed in Zule Xu et al., Picosecond Resolution Time-to-Digital Converter Using Gm-C Integrator and SAR-ADC, IEEE Transactions on Nuclear Science, vol. 61, No. 2, April 2014, but this implementation is not promising because it consumes too much power and has a limited dynamic range (consuming 20 mW for conversion rate of 10 MHz and having a limited dynamic range).
A time to digital converter that addresses at least some of the above mentioned problems is desired.
An important application for high performance phase locked loops is in frequency modulated continuous wave (FMCW) radar. One application for such radar devices is as proximity detectors in vehicles, for example for maintaining a safe distance from obstacles. In such applications it is necessary to produce a chirp signal with a highly linear variation in frequency with respect to time (because the frequency of the detected return signal is used to infer distance). For good distance resolution, a high degree of accuracy in the frequency output from the chirp generator is required. Furthermore, this application is challenging because of the high frequency tuning range and the required rate of change of the frequency. Typically there is a compromise between accuracy and rate of change and/or dynamic range in a phase locked loop. Known strategies for limiting the output noise of a phase locked loop, such as limiting the bandwidth of the phase locked loop are in conflict with the requirement for a large tuning range and high chirp speed.
A phase locked loop capable of overcoming at least some of the above mentioned problems is desired.